![]() ![]() Microelectronic Circuits - Fifth Edition Sedra/Smithħ sedr42021_0406.jpg Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt. ![]() Here, vGS is kept constant at a value > Vt. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Microelectronic Circuits - Fifth Edition Sedra/SmithĦ sedr42021_0405.jpg Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The device operates as a linear resistor whose value is controlled by vGS. 4.3 when the voltage applied between drain and source, vDS, is kept small. Microelectronic Circuits - Fifth Edition Sedra/Smithĥ sedr42021_0404.jpg Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. Note that the depletion region is not shown (for simplicity). Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. ![]() The device acts as a resistance whose value is determined by vGS. Microelectronic Circuits - Fifth Edition Sedra/SmithĤ sedr42021_0403.jpg Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. An n channel is induced at the top of the substrate beneath the gate. Microelectronic Circuits - Fifth Edition Sedra/Smithģ sedr42021_0402.jpg Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm. 2 sedr42021_0401a.jpg Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view (b) cross-section. ![]()
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